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Features
* * * * * * * * * * * *
AM/FM Tuner Front End with Integrated PLL AM Up-conversion System (AM-IF: 10.7 MHz) FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz Fast Fractional PLL (Lock Time < 1 ms) Inclusive Spurious Compensation Fast RF-AGC, Programmable in 1-dB Steps Fast IF-AGC, Programmable in 2-dB Steps Fast Frequency Change by 2 Programmable N-divider Two DACs for Automatic Tuner Alignment High S/N Ratio 3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers-compatible)
AM/FM Front End IC T4260
Electrostatic sensitive device. Observe precautions for handling.
Description
The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip solution based on Atmel's high-performance BICMOS II technology. The low-impedance driver at the IF output is designed for the A/D of a digital IF. The fast tuning concept realized in this part is based on patents held by Atmel and allows lock times less than 1 ms for a jump over the FM band with a step width of 12.5 kHz. The AM upconversion and the FM down-conversion allows an economic filter concept. An automatic tuner alignment is provided by built-in DACs for gain and offset compensation. The frequency range of the IC covers the FM broadcasting band as well as the AM band. The low current consumption helps the designers to achieve economic power consumption concepts and helps to keep the power dissipation in the tuner low.
Pin Description
Figure 1. Pinning SSO44
RFAGCFM REFFREQ RFAGCA1 IFAGCFM MXAMOA MXAMOB MXFMOB MXFMOA IFAGCA1 IFOUTA IFOUTB IFINAM GNDPLL IFINFM VRPLL
IFREF
GNDT
DATA
VST
VRT
CLK 24 OSCB 21
32
31
30
29
28
33
43
42
41
40
39
38
37
44
36
35
34
27
26
25
11
3
1
2
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
OSCE
SW1
20
SW2/AGC
RFAGCA2
FMAGCO
IFAGCA2
AMAGCO
MXFMIB
MXAMIB
MXFMIA
MXAMIA
OSCGND
OSCBUF
GNDRF
VRVCO
DAC1
DAC2
VSPLL
VTUNE
FMLF
AMLF
22
23
EN
Rev. 4528D-AUDR-09/02
1
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol DAC1 DAC2 FMAGCO MXFMIA MXFMIB GNDRF MXAMIB MXAMIA AMAGCO IFAGCA2 SW2/AGC RFAGCA2 SW1 VRVCO VSPLL FMLF AMLF VTUNE OSCGND OSCE OSCB OSCBUF EN CLK DATA VRPLL REFFREQ GNDPLL IFOUTB IFOUTA IFAGCFM IFAGCA1 RFAGCFM IFREF IFINAM IFINFM VRT GNDT MXAMOB MXAMOA VST RFAGCA1 MXFMOA MXFMOB Function DAC1 output DAC2 output FM AGC current FM mixer input A FM mixer input B RF ground AM mixer input B AM mixer input A AM AGC current AM IF-AGC filter 2 Switch 2 / AM AGC voltage RF AM-AGC filter 2 Switching output 1 VCO reference voltage PLL supply voltage FM loop filter AM loop filter Tuning voltage Oscillator ground Oscillator emitter Oscillator base Oscillator buffer output / input 3-wire bus Enable 3-wire bus Clock 3-wire bus Data PLL reference voltage PLL reference frequency PLL ground IF output B IF output A FM IF-AGC filter AM IF-AGC filter 1 RF FM-AGC filter IF amplifier reference input IF amplifier AM input IF amplifier FM input Tuner reference voltage Tuner ground AM mixer output B AM mixer output A Tuner supply voltage RF AM-AGC filter 1 FM mixer output A FM mixer output B
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Figure 2. Block Diagram
MXFMOB MXAMOA MXFMOA MXAMOB 43 44 39 40 IFINAM IFREF ININFM 34 35 36 IFAGCFM IFAGCA2 IFOUTA IFOUTB IFAGCA1 29 30 31 10 32 41 37 RF/IF SUPPLY 4 5 6 7 8 PLL SUPPLY AGC 15 26 28 VSPLL VRPLL GNDPLL 38 14 MXFMIA MXFMIB GNDRF MXAMIB MXAMIA VST VRT GNDT VRVCO
RFAGCA1 RFAGCFM RFAGCA2
42 33 12 AGC
DIV BUS
23 24 25 11
EN CLK DATA SW2/AGC SW1 DAC2 DAC1
AMAGCO FMAGCO
AM 9 3
FM
13 SW-AMLF PD R DIV VCO 2 1
N DIV
22 OSCBUF
21 20 19 OSCE OSCB OSCGND
27 REFFREQ
16 FMLF
17 AMLF
18 VTUNE
Functional Description
The T4260 implements an AM up-conversion reception path from the RF input signal to the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the LO frequency to the AM mixer. The FM reception path generates the same LO frequency from the RF input signal by a down-conversion to the IF output. The IF A/D output is designed for digital signal processing. The IF can be chosen in the range of 10 MHz to 25 MHz. Automatic gain control (AGC) circuits are implemented to control the preamplifier stages in the AM and FM reception paths. For improved performance, the PLL has an integrated special 2-bit shift fractional logic with spurious suppression that enables fast frequency changes in AM and FM mode by a low step frequency (fPDF). In addition, two programmable DACs (Digital to Analog Converter) support the alignment via a microcontroller. For a double-tuner concept, external voltage can be applied at the input of the DACs, the internal PLL can switched off and the OSC buffer (output) can also be used as input. Several register bits (Bit 0 to Bit 145) are used to control the circuit's operation and to adapt certain circuit parameters to the specific application. The control bits are organized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the 3-wire bus protocol. The bus protocol and the bit-to-register mapping is described in the section "3-wire Bus Description". The meaning of the control bits is mentioned in the following sections.
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Absolute Maximum Ratings
All voltages are referred to GND
Parameters Analog supply voltage Ambient temperature range Storage temperature range Junction temperature Pins 15 and 41 Maximum power consumption Symbol VST, VSPLL Ptot Tamb Tstg Tj Value 10 1.0 -40 to +85 -40 to +150 150 Unit V W C C C
Thermal Resistance
Parameters Junction ambient, soldered to PCB Symbol RthJA Value 52 Unit K/W
Operating Range
Parameters Supply voltage range Supply current Ambient temperature Oscillator frequency Note: Pin 21
(1)
Symbol Pins 15 and 41 Pins 15 and 41 VST, VSPLL IS Tamb Rfi
Min. 8 70 -40 60
Typ. 8.5
Max. 10 100 85 175
Unit V mA C MHz
1. VST and VSPLL must have the same voltage.
Electrical Characteristics
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25C
No. 1 1.1 1.2 Parameters PLL Divider Programmable R-divider Programmable (VCO) Ndivider (1 kHz step frequency) Reference oscillator input voltage Reference frequency Settling time in FM mode (switching from 87.5 MHz to 108 MHz or vice versa) 14-bit register 2- 18-bit register switchable via Bit 5 f = 0.1 MHz to 3 MHz FM AM fPD = 50 kHz IPD = 2 mA 3 16,383 A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
3
262,143
A
1.3 1.4 1.5
27
100 120 120 150 2,850 10,000 10,000
mVrms kHz kHz
B
1
ms
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25C
No. 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 4 4.1 4.2 4.3 4.4 4.5 4.6 5 5.1 5.2 5.3 6 6.1 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 Parameters AMLF/FMLF Output current 1 Output current 2 Output current 3 Output current 4 Leakage current VTUNE Saturation voltage LOW Saturation voltage HIGH DAC1, DAC2 Output current Output voltage Maximum offset range Minimum offset range Maximum gain range Minimum gain range Oscillator Frequency range Fractional frequency range Buffer output Oscillator Input Input voltage FM Mixer Frequency range Input IP3 Input impedance Input capacitance Noise figure Conversion transconductance AM Mixer (Symmetrical Input) Frequency range Input IP3 0.075 133 26 MHz dBV B C F 2.6 14 3.1 3.6 75 133 3.5 4 163 MHz dBV kW pF dB mS B C D D C D (1) 21 VOSC 150 mVrms A Fractional mode 21 21 22 60 60 150 170 140 MHz MHz mVrms B A C offset = 0, gain = 58 offset = 127, gain = 58 gain = 255, offset = 64 gain = 0, offset = 64 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 IDAC1,2 VDAC1,2 0.3 0.9 0.9 2.06 0.63 0.98 -0.98 2.09 0.67 1 VS-0.6 1.1 -1.1 2.13 0.73 mA V V V D A A (1) A (1) A (1) A (1) VSATH = (VA-VPDOFM) VSATH = (VA-VPDOFM) 18 18 VSATL VSATH 100 200 400 500 mV mV C C FMLF, AMLF = 1.8 V FMLF, AMLF = 1.8 V FMLF, AMLF = 1.8 V FMLF, AMLF = 1.8 V FMLF, AMLF = 1.8 V 16, 17 16, 17 16, 17 16, 17 16, 17 40 80 850 1650 50 100 1000 2000 60 120 1250 2450 10 A A A A nA A (1) A (1) A (1) A (1) A (1) Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25C
No. 8.3 8.4 8.5 9 9.1 9.2 10 10.1 10.2 10.3 Parameters Input impedance Noise figure Conversion transconductance Isolation Isolation AM-FM IF suppression RF-AGC Frequency range Output current Output current time constant RF-AGC AM threshold (programmable with Bit 12 - Bit 15) FM AM FM AM FM rising FM falling AM symmetrical 88 dBV 89 dBV 90 dBV 91 dBV 92 dBV 93 dBV 94 dBV 95 dBV 96 dBV 97 dBV 98 dBV 99 dBV 100 dBV 101 dBV 102 dBV 103 dBV 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 75 0.075 5 5 2 50 40 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 107 163 26 MHz MHz mA mA ms ms ms dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV A B 40 40 dB dB C C F 2.6 Test Conditions Pin Symbol Min. Typ. 2.5 10 3.1 3.6 Max. Unit kW dB mS Type* D C D (1)
C A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1)
10.4
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25C
No. 10.5 Parameters RF-AGC FM threshold (programmable with Bit 12 - Bit 15) Test Conditions 91 dBV 92 dBV 93 dBV 94 dBV 95 dBV 96 dBV 97 dBV 98 dBV 99 dBV 100 dBV 101 dBV 102 dBV 103 dBV 104 dBV 105 dBV 106 dBV 11 11.1 11.2 11.3 IF Amplifier Frequency range Output voltage Distortion (2-tone IM3) Gain (programmable in 2-dB steps) Input impedance IF-AGC IF-AGC AM/FM threshold (programmable with Bit 0 - Bit 2) 109 dBV 111 dBV 113 dBV 115 dBV 117 dBV 118 dBV 119 dBV 121 dBV 12.2 12.3 AGC dynamic range AGC time constant (external capacity 100 nF) IF Gain FM rising FM falling AM symmetrical 29/30 29/30 29/30 29/30 29/30 29/30 29/30 29/30 108 110 111 113 116 117 118 120 109 111 113 115 117 118 119 121 TBD 16 4 200 112 114 115 117 121 122 123 126 dBV dBV dBV dBV dBV dBV dBV dBV dB s ms ms A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) B D f1 = 10.7 MHz f2 = 10.75 MHz RL = 2 300 W Minimum gain Maximum gain FM AM 36, 35 10 117 55 12 42 330 2500 25 MHz dBV dB dB dB W W A B A Pin 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 Symbol Min. 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Typ. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Max. 93 95 96 96 98 99 102 101 102 104 104 105 106 107 108 109 Unit dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV dBV Type* A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1) A (1)
11.4 11.5 12 12.1
A D
13
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25C
No. 13.1 Parameters IF gain (programmable with Bit 6 - Bit 9) Test Conditions 12 dB 14 dB 16 dB 18 dB 20 dB 22 dB 24 dB 26 dB 28 dB 30 dB 32 dB 34 dB 36 dB 38 dB 40 dB 42 dB 14 14.1 14.2 14.3 15 15.1 15.2 15.3 16 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 SWO1 (Open Drain) Output voltageLOW Output leakage current HIGH Maximum output voltage SW2/AGC (Open Drain in Switch Mode) Output voltage LOW Output leakage current HIGH Maximum output voltage 3-wire Bus, ENABLE, DATA, CLOCK Input voltage Clock frequency Period of CLK Rise time EN, DA, CLK Fall time EN, DA, CLK Set-up time Hold time EN Hold time DA High Low 23-25 24 24 23-25 23-25 23-25 23 25 tH tL tR tF tS tHEN tHDA 100 250 0 250 250 400 100 VBUS VBUS 2.7 -0.3 5.3 0.8 1.0 V V MHz ns ns ns ns ns ns ns A A B C C C C C C C I = 1 mA, V11 = 6 V 11 11 11 VSWOL IOHL 6 100 160 200 10 mV A V A A C I = 1 mA, VSWO1 = 8.5 V 13 13 13 VSWOL IOHL 8.5 100 160 200 10 mV A V A A C Pin Symbol Min. 9 12 14 17 17 19 21 23 25 27 29 31 33 35 37 39 Typ. 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 Max. 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Type* A (1) A (1) A (1) C (1) A (1) C (1) C (1) C (1) A (1) C (1) C (1) C (1) C (1) C (1) C (1) A (1)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40C to +85C) but are tested at +25C
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3-wire Bus Description
The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all bits of one register. The different registers available (see chapter "3-wire Bus Data Transfer") are addressed by the length of the command (number of transmitted bits) and by two address bits that are unique to each register of a given length. 8-bit registers are programmed by 8-bit commands, 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24bit commands. Each bus command starts with a falling edge on the enable line (EN) and ends with a rising edge on EN. EN has to be kept LOW during the bus command. The sequence of transmitted bits during one command starts with the MSB of the first byte and ends with the LSB of the last byte of the register addressed. To transmit one bit (0/1), DATA has to be set to the appropriate value (LOW/HIGH) and a HIGH-to-LOW transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the falling edges of CLK. The number of HIGH-to-LOW transitions on CLK during the LOW period of EN is used to determine the length of the command. Figure 3. 3-wire Pulse Diagram
8-bit command
EN DATA CLK
MSB BYTE 1 LSB
16-bit command
EN DATA CLK
MSB BYTE 1 LSB MSB BYTE 2 LSB
24-bit command
EN DATA CLK
MSB BYTE 1 LSB MSB BYTE 2 LSB MSB BYTE 3 LSB
e.g. R-Divider
27 26 25 24 23 2
2
21
20
X
X
2
13
2
12
2 11
2
10
29
28
1
0 Addr.
PDFM PDAM
Fract. 2
3
2
2
2
1
2
0
R-Divider
VCO-Divider
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Figure 4. 3-wire Bus Timing Diagram
tF tR VHigh tS tR Data tHDA tS tR Clock tF VHigh VLow tH tL tF VHigh VLow tHEN VLow
Enable
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3-wire Bus Data Transfer
Table 1. Control Registers
A24_10
MSB BYTE 1 LS B MSB BYTE 2 LS B MSB PDA M/P DFM 1/0 145 BYTE 3 Fractio nal 0/1 144 23 14 3 LS B Divider VCO 22 14 2 21 14 1 20 14 0
R-Divider 27 131 26 130 25 129 24 128 23 127 22 126 21 125 20 124 x 139 x 138 213 137
R-Divider 212 136 211 135 210 134 29 133 28 132
ADDR. 1 x 0 x
A24_01
MSB BYTE 1 N2-Divider 27 109 26 108 25 107 24 106 23 105 22 104 21 103 20 102 215 117 214 116 213 115 LS B MSB BYTE 2 N2-Divider 212 114 211 113 210 112 29 111 28 110 LS B MSB ADDR. 0 x 1 x x 0 123 BYTE 3 x 0 122 x 0 12 1 x 0 12 0 LS B N2-Divider 217 11 9 216 11 8
A24_00
MSB BYTE 1 N1-Divider 27 87 26 86 25 85 24 84 23 83 22 82 21 81 20 80 215 95 214 94 213 93 LS B MSB BYTE 2 N1-Divider 212 92 211 91 210 90 29 89 28 88 LS B MSB ADDR. 0 x 0 x x 0 101 BYTE 3 x 0 100 x 0 99 x 0 98 LS B N1-Divider 217 97 216 96
A16_11
MSB BYTE 1 DAC2-Gain 27 73 26 72 25 71 24 70 23 69 22 68 21 67 20 66 LS B MSB ADDR. 1 x 1 x x 79 x 78 x 77 x 76 x 75 x 74 BYTE 2 LSB
A16_10
MSB BYTE 1 LS B MSB SWAMLF 1= stand ard 65 BYTE 2 Osc.Buffe r ON/ OFF 64 Low c. CP HI/L O 63 High c.C P HI/L O 62 SWimpul se ON/ OFF 61 LSB SWwire ON/O FF 60
DAC2-Offset
ADDR.
x 59
26 58
25 57
24 56
23 55
22 54
21 53
20 52
1 x
0 x
A16_01
MSB BYTE 1 DAC1-Gain 27 45 26 44 25 43 24 42 23 41 22 40 21 39 20 38 LS B MSB ADDR. 0 x 1 x x 51 x 50 x 49 BYTE 2 1=SW2 0=AGC 1/0 48 SW2 1=low 1/0 47 LSB SW1 1=low 1/0 46
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A16_00
MSB BYTE 1 LS B MSB BYTE 2 Lock det. sensitiv. 1/0 35 1/0 34 Sh_L D_Di rect 1/0 33 LSB Sh_ Direct 1/0 32
DAC1-Offset x 31 26 30 25 29 24 28 23 27 22 26 21 25 20 24
ADDR. 0 x 0 x
Lock det. filter 1/0 37 1/0 36
A8_11
MSB BYTE 1 Delay time high cur. CP2 ON/ OFF 23 HI/L O 22 Delay time high cur. CP1 ON/ OFF 21 HI/ LO 20 HCD EL/ Direc t 1/0 19 LSB HCD EL/ _Dire ct 1/0 18
ADDR.
1 x
1 x
A8_10
MSB ADDR. 1 x 0 x AM/F M 1/0 17 BYTE 1 IFAGC 1/0 16 23 15 22 14 RF-AGC 21 13 20 12 LSB
A8_01
MSB ADDR. 0 x 1 x IF-IN AM/F M 11 BYTE 1 VCO HI/L O 10 23 9 22 8 IF-Gain 21 7 20 6 LSB
A8_00
MSB ADDR. 0 x 0 x N2/N 1 1/0 5 BYTE 1 PLL ON/ OFF 1/0 4 PD TE/ PD 1/0 3 22 2 IF-AGC 21 1 20 0 LSB
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Bus Control
IF-AGC
The IF-AGC controls the level of the IF signal that is passed to the external ceramic filter and the IF input (AM Pin 35 or FM Pin 36 and Pin 34). In AM mode the time constant can be selected by the external capacitors at Pin 32 (IFAGCA1) and Pin 10 (IFAGCA2) and in FM mode by an external capacitor at Pin 31 (IFAGCFM). In AM mode, the double pole (by the capacitors at Pin 32 and Pin 10) allows a better harmonic distortion by a lower time constant. The IF-AGC threshold can be controlled by setting Bits 0 to 2 as given in Table 2. Table 2. IF-AGC Threshold
IF-AGC B2 B1 B0
109 dBV 111 dBV 113 dBV 115 dBV 117 dBV 118 dBV 119 dBV 121 dBV
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
The IF-AGC ON/OFF can be controlled by Bit 16 as given in Table 3. Table 3. IF-AGC
IF-AGC ON/OFF B16
IF-AGC ON IF-AGC OFF
0 1
PD Test
Only in FM mode, the locked and unlocked condition of the PLL can be signaled at the AMLF-Pin (Pin 17) by activation of PD test (Bit 3 = 1). The locked PLL (in FM mode) is signaled by a high level (5 V) and the unlocked PLL by a low level (0 V) at Pin 17. For the use of PD test, it is necessary to interrupt the external AM loop filter to VTUNE (Pin 18) and to FMLF (Pin 16). Moreover, the loop filter operating mode has to be set to PDFM active (Bit 145 = 0). Table 4. PD-Test Mode
PD TE/PD B3
Pin 17 = AMLF output (standard) Pin 17 = Lock detect output
0 1
N1/N2
The N2/N1 Bit controls the active N-divider. Only one of the two N-Divider can be active. The N1-Divider is activated by setting Bit 5 = 0, the N2-Divider by setting Bit 5 = 1. Table 5. N-Divider
N2/N1 B5
N1-divider active N2-divider active
0 1
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IF Amplifier
The IF gain amplifier can be used in AM and FM mode to compensate the loss of the external ceramic bandfilters. The IF gain can be controlled in 2-dB steps by setting Bit 6 to Bit 9 as given in Table 6. Table 6. IF Gain
IF Gain B9 B8 B7 B6
12 dB 14 dB 16 dB 18 dB 20 dB ... 40 dB 42 dB
0 0 0 0 0 ... 1 1
0 0 0 0 1 ... 1 1
0 0 1 1 0 ... 1 1
0 1 0 1 0 ... 0 1
The selection of the IF amplifier input can be controlled by Bit 11 as given in Table 7. Table 7. IF-IN Operating Mode
IF-IN AM/FM B11
IF-IN FM IF-IN AM
0 1
REMARK: The AM input (Pin 35) has an input impedance of 2.5 kW for matching with a crystal filter. The FM input (Pin 36) has an input impedance of 330 W for matching with a ceramic filter.
VCO
The VCO HI/LO function is controlled by means of Bit 10. Table 8. VCO Operating Mode
VCO HI/LO B10
VCO high current VCO low current
0 1
RF-AGC
The AM and FM RF-AGC controls the current into the AM and FM pin diodes (FM Pin 3 and AM Pin 9) to limit the level at the AM or FM mixer input. If the level at the AM or FM mixer input exceeds the selected threshold, then the current into the AM or FM pin diodes increases. If this step is not sufficient in AM mode, the source drain voltage of the MOSFET (Pin 11) can be decreased. In AM mode, the time constants can be selected by the external capacitors at Pin 42 (RFAGCA1) and at Pin 12 (RFAGCAM2) and in FM mode by an external capacitor at Pin 33 (RFAGCFM). In AM mode, the double pole (by the capacitors at Pin 42 and Pin 12) allows a better harmonic distortion by a lower time constant. The RF-AGC can be controlled in 1-dB steps by setting the Bits 12 to 15. The values for FM and AM are controlled by Bit 17.
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Table 9. RF-AGC
RF-AGC AM RF-AGC FM B15 B14 B13 B12
88 dB 89 dB 90 dB 91 dB 92 dB ... 102 dB 103 dB
91 dB 92 dB 93 dB 94 dB 95 dB ... 105 dB 106 dB
0 0 0 0 0 ... 1 1
0 0 0 0 1 ... 1 1
0 0 1 1 0 ... 1 1
0 1 0 1 0 ... 0 1
Reception Mode
There are two different operation modes, AM and FM, which are selected by means of Bit 17 and Bit 145 according to Table 1 and Table 2. In AM mode (Bit 17 = 1), the AM mixer, the AM RF-AGC, the AM divider (prescaler) and the IF AM amplifier (input at Pin 35) are activated. In FM mode (Bit 17 = 0), the FM mixer, the FM RF-AGC and the IF FM amplifier (input at Pin 36) are activated. In AM or FM reception mode, Bit 145 has to be set to the corresponding mode. The buffer amplifier input can be connected to Pin 16 (with the external FM loop filter) by Bit 145 = 0 and to Pin 17 (with the external AM loopfilter) by Bit 145 = 1. The AM/FM function for the tuner part is controlled by Bit 17 as given in Table 10. Table 10. Tuner Operating Modes
AM/FM B17
FM AM
0 1
PLL
The PLL can switch off by Bit 4 = 0. In this case, the N-Divider signal is internally connected to ground. Table 11. PLL Mode
PLL ON/OFF B4
PLL OFF PLL ON
0 1
There are two registers, HCDEL 1 (Bits 20 and 21) and HCDEL 2 (Bits 22 and 23), to control the delay time of the high-current charge pump and to deactivate them. Bit 18 (HCDEL_Direct) and Bit 19 (HCDEL_LD/ Direct) determine whether register HCDEL 1 or 2 is used. If Bit 19 is 0, then Bit 18 is used to select between HCDEL 1 and HCDEL 2. If Bit 19 is 1, and no lock detect is signaled, register HCDEL 1 is used, if Bit 19 is 1 and a lock detect is signaled, then HCDEL 2 is used. Switching to HCDEL 1 can be limited to one time per N1/N2 change by setting Bit 18 to Bit 19.
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Table 12. High-current Charge Pump Delay Time Register
HCDEL 1/2 Select Mode HCDEL_ LD/ Direct B19 HCDEL_ Direct B18
Direct HCDEL 1 Direct HCDEL 2 HCDEL = lock_detect HCDEL = lock detect, only 1 change per N1/N2 change
0 0 1 1
0 1 0 1
If Bits 20 and 21 (HCDEL 1) or Bits 22 and 23 (HDCEL 2) are both set to 0, then the high-current charge pump is deactivated. Otherwise, the delay time can be selected as described in Table 13. Table 13. Delay Time of HCDEL Register
High-current Charge Pump B21/B23 B20/B22
OFF Delay time 5 ns Delay time 10 ns Delay time 15 ns
0 0 1 1
0 1 0 1
The VCO frequency N-divided signal and the reference frequency R-divided signal (step frequency) will be compared. If the delay time between both signals is lower than the choosen time (LD_sens) the PLL lock detect is signalized. The lock detect sensitivity is controlled by Bits 34 and 35 as follows. Table 14. Lock Detect Sensitivity Time
LD_sens B35 B34
9 ns 6 ns 5 ns 4 ns
0 0 1 1
0 1 0 1
REMARK:
The values are the phase differences on the phase detector.
The Shift-Direct function can also be controlled by Bit 32 and Bit 33 as follows. If Bit 33 = 0 and Bit 32 = 0, the R/N-divider is shifted by two bits to the right. Bit 33 controls the manual or the lock detect-controlled 2-bit shift of the R/N-divider. A divider 2-bit shift (Bit 33 = 0 and Bit 32 = 0) allows faster frequeny changes by using a four times higher step frequeny (e.g., fPDF = 50 kHz instead of fPDF = 12.5 kHz). If the PLL is locked (after the frequency change), the normal step frequency (e.g., fPDF = 12.5 kHz) will be active again. If no 2-bit shift is used (Bit 33 = 0 and Bit 32 = 1), the frequeny changes will be done with the normal step frequency (12.5 kHz).
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Table 15. Manual and Lock Detect Shift Mode
Sh_LD Control Sh_LD/Direct B33 Sh_Direct B32
Dividers 2-bit shift No shift Sh = Lock_detect Sh = Lock_detect, only 1 change per N1/N2 change
0 0 1 1
0 1 0 1
The lock detect filter is controlled by Bits 36 and 37 as given in Table 16. Table 16. LD Filter
LD Filter B37 B36
Direct 1 clock delay 2 clock delay 3 clock delay
0 0 1 1
0 1 0 1
REMARK: Before the lock detect signal becomes valid, the phase comparison must be valid 0, 1, 2, 3 periods of fPFD.
SW1 (Pin 13)
The switching output SW1 (Pin 13) is controlled by Bit 46 as given in Table 17. Table 17. Switching Output
SW1 B46
High Low
0 1
REMARK:
SW1 is an open-drain output.
Figure 5. Internal Components at SW1
SW1
SW2/AGC (Pin 11)
The Pin SW2/AGC works as a switching output (open drain, Pin 11) or as an AM AGCcontrol pin to control the cascade stage of an external AM-preamplifier. The SW2/AGC is controlled by Bits 47 and 48 as given in Table 18.
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Table 18. Switching Output 2 / AGC Mode
SW2/AGC B48 B47
AGC function High Low
0 1 1
X 0 1
REMARK:
In AGC mode, the output voltage is 6 V down to 1 V.
Figure 6. Internal Components at SW2/AGC
VS AGC SWO/AGC SW2
Test Mode
A special test mode is implemented for final production test only. This mode is activated by setting Bit 123 = 1. This mode is not intended to be used by customer application. For normal operation Bit 123 has to be set to 0. Table 19. Test Mode
Test Mode B123
ON OFF
1 0
AM Mixer
The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore, an AM prescaler is implemented to generate the necessary LO frequency from the VCO frequency. The VCO divider can be controlled by the Bits 140 to 143 as given in Table 20. (The VCO divider is only active in AM mode) Table 20. Divider Factor of the AM Prescaler
Divider AM Prescaler B143 B142 B141 B140
Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 x
0 0 1 1 0 0 1 1 x
0 1 0 1 0 1 0 1 x
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FM Mixer PLL Loop Filter
In the FM mixer stage, the FM reception frequency is down-converted to the IF frequency. The VCO frequency is used as LO frequency for the mixer. The PLL loop filter selection for AM and FM mode can be controlled by Bit 145 as given in Table 21. Table 21. Loop Filter Operating Mode
PDAM/PDFM B145
PDFM active PDAM active
0 1
Fractional Mode
The activated fractional mode (Bit 144 = 0) in connection with the direct shift (Bit 32 = 0) allows fast frequency changes (with the help of the 2-bit shift) with a four times higher step frequency. After the frequency change, the normal step frequency is active again. If the fractional mode is deactivated (Bit 144 = 1) and direct shift mode is active, (Bit 32 = 0) the VCO frequency is set to the next lower frequency which is many times the amount frequency of 4 times step frequency. This means that the 2 shifted bits of the active N-Divider are not used in this mode. The shift bits are interpreted as logic 0. The fractional mode with direct shift mode deactivated (Bit 32 = 1) allows normal frequency changes with a step frequency of 12.5 kHz. Table 22. Fractional Mode
Fractional B144
ON OFF
0 1
Spurious Suppression
In fractional and direct shift mode the spurious suppression is able by SW wire and SW impulse. Table 23. Spurious Suppression by SW Wire
SW Wire B60
OFF ON
0 1
Table 24. Spurious Suppression by Correction Current Charge Pump
SW Impulse B61
OFF ON
0 1
Charge Pump (AMLF/FMLF)
AMLF/FMLF is the current charge pump output of the PLL. The current can be controlled by setting the Bits 62 and 63. The loop filter has to be designed correspondingly to the chosen pump current and the internal reference frequency. During the frequency change, the high-current charge pump (Bit 62) is active to enable fast frequency changes. After the frequency change, the current will be reduced to guarantee a high S/N ratio. The low-current charge pump (Bit 63) is then active. The high current charge pump can also be switched off by setting the bits of the active HCDEL register to 0 (Bit 20 and Bit 21 [HCDEL 1] or Bit 22 and Bit 23 [HCDEL 2]). The current of the high-current charge pump is controlled by Bit 62 as given in Table 25.
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Table 25. High-current Charge Pump
High-current Charge Pump B62
1 mA 2 mA
0 1
The current of the low-current charge pump is controlled by Bit 63 as given in Table 26. Table 26. Low-current Charge Pump
Low Current Charge Pump B63
50 A 100 A
0 1
External Voltage at AMLF The oscillator (Pin 22) can be switched on/off by Bit 65. It is possible to use the oscillator buffer as an input or as an output. At the AMLF (Pin 17), an external tuning voltage can (Oscillator)
be applied (Bit 65 = 0). If this is not done, the IC operates in standard mode (Bit 65 = 1). The oscillator, oscillator buffer and the AMLF are controlled by the Bits 65 and 64 as given in Table 27. Table 27. Oscillator Operating Modes
Oscillator Oscillator Buffer AMLF (Pin 17) B65 B64
OFF ON ON
INPUT OFF OUTPUT
INPUT f. DAC's AMLF (standard) AMLF (standard)
0 1 1
X 0 1
DAC1, 2 (Pins 1, 2)
For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by setting gain and offset values. The principle of the operation is shown in Figure 7. The gain is in the range of 0.67 VTune to 2.09 VTune. The offset range is +0.98 V to -0.98 V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filter and the IF filter. For alignment, offset and gain are set for having the best tuner tracking. Figure 7. Block Diagram of DAC1, 2
VTUNE Gain +/DAC1, 2
Offset
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The gain of DAC1 and DAC2 has a range of approximately 0.67 V(VTUNE) to 2.09 V(TUNE). This range is divided into 255 steps. One step is approximately (2.090.67)/255 = 0.00557 V(TUNE). The gain of DAC1 can be controlled by the Bits 38 to 45 (20 to 27) and the gain of DAC2 can be controlled by the Bits 66 to Bit 73 (20 to 27) as given in Table 28. Table 28. Gain of DAC1, 2
Gain DAC1 Approximately Gain DAC2 Approximately B45 B73 B44 B72 B43 B71 B42 B70 B41 B69 B40 B68 B39 B67 B38 B66 Decimal Gain Decimal Gain
0.6728 V(TUNE) 0.6783 V(TUNE) 0.6838 V(TUNE) 0.6894 V(TUNE) ... 0.9959 V(TUNE) ... 2.0821 V(TUNE) 2.0877 V(TUNE) 2.0932 V(TUNE)
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 1 ... 1 1 1
0 0 0 0 ... 1 ... 1 1 1
0 0 0 0 ... 1 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 1 1 ... 1 ... 0 1 1
0 1 0 1 ... 0 ... 1 0 1
0 1 2 3 ... 58 ... 253 254 255
Offset = 64 (intermediate position)
The offset of DAC1 and DAC2 has a range of approximately +0.98 V to -0.99 V. This range is divided into 127 steps. One step is approximately 1.97 V/127 = 15.52 mV. The offset of DAC1 can be controlled by the Bits 24 to Bit 30 (20 to 26) and the offset gain of DAC2 can be controlled by the Bits 52 to Bit 58 (20 to 26) as given in Table 29. Table 29. Offset of DAC1, 2
Offset DAC1 Approximately Offset DAC2 Approximately B30 B58 B29 B57 B28 B56 B26 B55 B26 B54 B25 B53 B24 B52 Decimal Offset Decimal Offset
0.9815 V 0.9659 V 0.9512 V 0.9353 V ... -0.0120 V ... -0.9576 V -0.9733 V -0.9890 V
0 0 0 0 1 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 1 1 ... 0 ... 0 1 1
0 1 0 1 ... 0 ... 1 0 1
0 1 2 3 ... 64 ... 125 126 127
Gain = 58 (intermediate position)
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Permitted DAC Conditons
The internal operation amplifier of the DACs should not operate with a too high internal difference voltage at their inputs. This means that a voltage difference higher than 0.5 V at the internal OP input should be avoided in operation mode. The respective output OP in the DAC is necessary for the addition and amplification of the tuning voltage (at pin 18) with the desired voltage gain and offset value. If the tuning voltage reaches a high value e.g. 9 V, with a gain setting of 2 times VTune and an offset of +1 V, then the output OP of the DAC should reach the (calculated) voltage of 19 V. The supply voltage of e.g. 10 V, however, limits the output voltage (of the DAC) to 10 V maximum. Due to the (limiting) supply voltage and the internal gain resistance ratio of 6 , the missing 9 V (calculated voltage - Vs) cause a voltage of 1.5 V at the OP input. This condition may not remain for a longer period of time. As long as the calculated DAC output voltage value does not exceed the supply voltage value by more than 3 V, no damages should occur during the product's lifetime as the input voltage of the internal OP input voltage does not exceed 0.5 V. VTune x DAC gain factor + DAC offset < Vs + 3 V (9 V x 2 + 1 V) < 10 V + 3 V (condition not allowed) This means when having a gain factor of 2 and an offset value of 1 V, the tuning voltage should not exceed 6 V. Maximum tuning voltage < (VS + 3 V - DAC offset) / DAC gain factor e.g.: maximum tuing voltage = (10 V + 3 V - 1 V) / 2 = 6 V It is also possible to reduce the gain or the offset value instead of (or along with) the tuning voltage.
Figure 8. Internal Components of DAC1, 2
VS
DAC1, 2
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Input/Output Interface Circuits
VTUNE, AMLF and FMLF (Pins 16-18)
VTUNE is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. Figure 9. Internal Components at VTune, AMLF and FMLF
VS VS
VTUNE
V5
AMLF/FMLF
EN, DATA, CLK (Pins 23-25)
All functions can be controlled via a 3-wire bus consisting of Enable, Data and Clock. The bus is designed for microcontrollers which can operate with 3-V supply voltage. Details of the data transfer protocol can be found in the chapter "3-Wire Bus Description". Figure 10. Internal Components at Enable, Data and Clock
V5
EN DATA CLK
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Application Information PLL Concept of U4257BM
The PLL architecture of the T4260 allows a fast tuning response time of approximately 1 ms, for a jump over the FM band of 87.5 MHz to 108 MHz, with a phase detector frequency (f PDF ) of 12.5 kHz in FM mode. This fast response time with the small f PDF frequency is achieved by a patented three-PLL concept. The functional blocks are listed below.
DPLL1 (PLL1)
DPLL1 is a digital PLL and consists out of the following stages: 14-bit R-Divider 18-bit N-Divider PFD (Phase Frequency Detector) Charge pump (50 A to 2000 A) Active loop amplifier Lock detector
Fractional PLL (PLL2)
This is a fractional PLL with a 2-bit wide accumulator and consists out of the following stages: 12-bit R-Divider 16-bit N/N+1-Divider PFD (Phase Frequency Detector) Charge pump (50 A to 2000 A) 2-bit accumulator Active loop amplifier Lock detector
DPLL2 (PLL3)
DPLL2 is a digital PLL containing the following stages: 12-bit R-Divider 16-bit N-Divider PFD (Phase Frequency Detector) Charge pump (50 A to 2000 A) Active loop amplifier Lock detector
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Figure 11. Block Diagram of the PLL Core
14 - BIT
LATCH R - DIV.
SWITCH
BIT 18, 19 BIT 32, 33 HCDEL 1 HCDEL 2
SHIFT 2 BIT
Fref
R - DIVIDER
LOCK - DET.
DELAYTIME high cur. CP
B145 AM / FM
AM - LOOP FILTER
PHASE DETECTOR
CHARGE PUMP
AM/FM FILTER
FM - LOOP FILTER
N / N+1 DIVIDER
PREAMP B62,63 B60,61
VCO
SHIFT 2 BIT
SWITCH N+1, N
B3
MUX N1 N2 2-BIT (LSB)
ACCU 2 - BIT
LATCH N - DIV 1
LATCH N - DIV 2
2- BIT
18 - BIT
18 - BIT
High-speed Tuning Concept
If the PLL core operates in locked mode, PLL1 (DPLL1) is active (tuned function mode). In this mode, a high S/N ratio is provided, but the lock time is approximately 4 ms with f PDF = 12.5 kHz (fPDF is the phase-detector frequency) and Pd cu = 2 mA (Pd cu is the charge pump current). For a fast tuning response, PLL2 (fractional PLL) or PLL3 (DPLL2) is used during the tuning time. The switch between the PLLs is controlled via the lock-detect signal or with a 3-wire-bus protocol. In the lock-detect controlled mode all function blocks are switched automatically, so no software protocols are necessary. In the PLL2 and PLL3 mode, the fPDF of 12.5 kHz is multiplied by four (fPDF = 50 kHz). Due to the higher fPDF frequency, a faster lock time is possible (approximately 1 ms for a tune from 98 MHz to 118 MHz). The higher fPDF for PLL2 and PLL3 is achieved by shifting the bits for N/R-divider two bits right. The bits are shifted simultaneously and synchronized with the phase-detector status. This shift is comparable with a fPDF frequency multiplication by four. PLL2, the fractional PLL, uses the two shifted bits of the N-divider for the fractional control. These bits are needed in the accumulator to control the N/N+1-divider control signal. In PLL3 mode the two LSB bits of the N/R-divider are not used, so an offset of the output frequency may occur.
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Control of Functions
All functions are controlled via 3-wire-bus protocols. The privileged control set is the lock-detect controlled mode for the PLL1 during lock time and PLL2 during tuning time. This function can be set by Bit 144 = 0 and Bit 33 = 1. Bits 18, 19, 32, 33 and 144 are the function mode bits. A detailed description of the bits meaning is found in the 3-wirebus description. For the calculation of the R/N-divider values, the PLL1 mode is valid, e.g., if the f ref (reference frequency) in FM mode is fref = 150 kHz, the R-divider for fPDF = 12.5 kHz is 150 kHz/ 12.5 kHz = 12. If the receiving frequency is f rec = 98 MHz, the N-divider is (98 MHz + fIF)/ 12.5 kHz = 8695. If the R-divider is shifted by two to the right, the R-divider is 3 and fPDF is 50 kHz. If the N-divider is shifted by two bits to the right, the N-divider is 2173 and frec is 97.9625 MHz. This output frequency is valid if PLL3 is used. In case of PLL2, the two LSB of the N-divider are used for fractional control and the frequency frec is then 98 MHz. REMARK: fIF = 10.6875 MHz
High-speed Tuning
The fractional mode (Bit 144 = 0) in connection with the direct shift mode (Bit 32 = 0) allows very fast frequency changes with four times the step frequency (50 kHz = 4 fPDF) at low frequency steps (e.g., fPDF = 12.5 kHz). In direct shift mode, the R- and the N-divider are shifted by 2 bits to the right (this corresponds to a R- and N-divider division by 4 or a step frequency multiplication by 4). Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of 34 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with fPDF = 12.5 kHz. If the FM receiving frequency is 103.2125 MHz (with e.g. f PDF = 12.5 kHz and fIF = 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a reference-frequency (fref) of 150 kHz. fVCO = fIF + frec = 10.7 MHz + 103.2125 MHz = 113.9125 MHz fPDF = fVCO / N = fref / R = 113.9125 MHz / 9113 = 150 kHz /12 = 12.5 kHz An important condition for the use of the fractional mode is an R-divider with an integer value after the division by 4 (R-dividers have to be a multiple of 4). After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called 1/4 fractional step because the modulo value of the N-divider is 0.25 = 1/4. In total, there are 4 different fractional 2-bit shift steps: full, 1/4, 1/2 and 3/4 step. If the fractional mode is switched off (Bit 144 = 1) during direct shift mode (Bit 32 = 0), the modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead of 2278.25). This means that the PLL locks on the next lower multiple frequency of 4 fPDF (in our case fPDF = 12.5 kHz). The new VCO frequency (fVCO) is then 113.9 MHz (instead of 113.9125 MHz in fractional mode). Also the PLL has additionally a special fractional logic which allows a good spurious suppression in the fractional and direct shift mode. Activating the wire switch (Bit 60 = 1) and the correction charge pump (Bit 60 = 1) the spurious suppression is active.
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Charge Pump Current Settings
Bit 62 (0 = 1 mA; 1 = 2 mA) allows to adjust the high current, which is active during a frequency change (if the delay time of the active HCDEL register is not switched off). A high charge pump current allows faster frequeny changes. After a frequency change, the current reduction is reduced (in locked mode) to the low current which is set by bit 63 (0 = 50 A; 1 = 100 A). A lower charge pump current guarantees a higher S/N ratio.
The high current charge pump can be switched off by the active HCDEL register bits. In this case, when HCDEL 1 is active and the bits 20 and 21 are 0 (HCDEL 1 delay time = off) or HCDEL 2 is active and the bits 22 and 23 are 0 (HCDEL 2 delay time = off), only the low current charge pump (current) is active in locked and in the frequency change mode.
AM Prescaler (Divider) Settings
The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore, an AM prescaler is implemented to generate the necessary LO from the VCO frequency. For the reception of the AM band, different prescaler (divider) settings are possible. Table 30 lists the AM prescaler (divider) settings and the reception frequencies.
fVCO = 98.2 MHz to 124 MHz fIF = 10.7 MHz frec = fVCO - fIF fVCO = AM prescaler x (frec + fIF) The following formula can also be useful by AM frequencies higher than 20 MHz: fVCO = AM prescaler x (frec - fIF) Table 30. AM Prescaler (Divider) Settings and the Reception Frequencies
Divider (AM Prescaler) Minimum Reception Frequency [MHz] Maximum Reception Frequency [MHz]
no divider Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10
87.5 38.4 22.033 13.85 8.94 5.667 3.329 1.575 0.211 0
113.3 51.3 30.633 20.3 14.1 9.967 7.014 4.8 3.078 1.7
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External Voltage at AMLF By using two ICs, for example, it is possible to operate the AMLF (Pin 17) of the second IC either with the tuning voltage (Vtune [Pin 18]), the DAC 1 voltage [Pin 1] or the DAC 2 (Pin 17)
voltage [Pin 2] from the first T4260. For voltage reduction at the AMLF [Pin 17], a voltage factor ratio of 100/16 (R1/R2) is required. This means that an applied voltage from 0.5 V at Pin 17 (AMLF) corresponds to a tuning voltage of 3.625 V. It is recommended to use R1 with 100 kW and R2 with 16 kW. The allowed range of R1 is 10 kW to 1 MW and 1.6 kW to 160 kW for R2. Figure 12. External Voltage at AMLF (Pin 17)
U4257BM Gain Vtune or DAC
R1
R2
AMLF U4257BM
The maximum input voltage at the AMLF input (pin 17) depends on the applied supply voltage as well as on the gain and offset settings. To avoid any damages during the product's lifetime, the following formulas regarding SWAMLF voltage, gain and offset settings have to be observed (see also chapter Permitted DAC Conditions). VSWAMLF x ([R1 + R2] / R2) x DAC gain factor + DAC offset < VS + 3 V (R1 + R2) / R2 = 7.25 This means when having a gain factor of 2 and an offset value of 1 V, the applied SWAMLF voltage should be limited to a voltage lower than 0.83 V. SWAMLF voltage < (VS + 3 V - DAC offset) / (DAC gain factor x 7.25) e.g.: maximum SWAMLF voltage = (10 V + 3 V - 1 V) / (2 x 7.25) = 0.83 V It is also possible to reduce the gain or offset instead (or along with) the SWAMLF voltage.
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Figure 13. Test Circuit
Test Point
1 DAC1 10n 2 DAC2 10n 3 FMAGCO 4 MXFMIA 10n 5 MXFMIB 6 GNDRF 7 MXAMIB 10n 8 MXAMIA 9 AMAGCO 10 IFAGCA2 11 SW2/AGC RFAGCA 12 2 13 SW1 14 VRVCO 100n
MXFMOB 44 330 MXFMOA 43 RFAGCA1 42 VST 41 MXAMOA 40 MXAMOB 39 GNDT 38 VRT 37 100n IFINFM 36 330 IFINAM 35 2k4 IFREF 34 RFAGCFM 33 100k IFAGCA1 32 100k IFAGCFM 31 IFOUTA 30 100 IFOUTB 29 GNDPLL 28 REFFREQ 27 VRPLL 26 10n DATA 25 CLK 24 EN 23 10n 100n VST 100n
3k
VSPLL
15 VSPLL 16 FMLF
100n 1n 5k1 17 AMLF 18 VTUNE 10k 5k6 19 OSCGND 1n 22p 20 OSCE 47p 21 OSCB 22 OSCBUF
15p
BUS
10n
10n
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4528D-AUDR-09/02
Figure 14. Application Circuit
P2 GNDT P3 GNDPLL C13 10uF KF2 IFoutA Bu2 IFoutB Bu3 C15 C14 100n C8 100n 38
GNDT
R2 180 R5 5R6 VST R1 P1 5R6 C1 10u C2 100n F2 C3 100p 44 43
MXFMOB MXFMOA
C4 1u R3 300
C7 100n
R8 2k2
KF1 F1 R6 300
REFFREQ Bu4 DATA P4 CLK P5 EN P6
100n
C9 100n C10 C11 C12 100n 220n100n 35
IFINAM
C5 220n 42
RFAGCA1
C6 47p 40 39
MXAMOA MXAMOB
41
VST
37 36
VRT IFINFM
34
IFREF
33 32
IFAGCA1 RFAGCA2 RFAGCFM
31
IFAGCFM
30
IFOUTA
29 28
IFOUTB GNDPLL
27
REFFREQ
26
VRPLL
25
DATA
24
CLK
23
EN
SW2/AGC
AMAGCO
FMAGCO
OSCGND
IFAGCA2
DAC1 P7 DAC2 P8
1 C16 10n
2
3
4
5
6 7 C29 100n C31 12p L2 100uH C32 6p8 C25 L3 4n7 2m2
8 9 C30 100n
10 11 C28 4u7
12 13 14 C37 C39 2u2 100n P15 SW1
15
16 17
18
19
20
21
C47 C48 P11 P12 P13 FM AM VT C40 15n C41 100n C42 1n C49 6p8 F5 22p 47p
22 OSCBUF Bu5
C17 10n R14 68k F3 R11 CD1 68k C23 C24 1n 6p8 C22 18p BB804 R9 470 R10 47k 10p C19 L1 T1 C18 2u2 BFR93A 10n R13 1k C27 R12 68k C21 C20 10n 27p F4 BB804 CD2 D1 C26
C50 OSCB Bu4 1n
BC 848 T3 R16 2k7 C38 100n
R24 6k2
C43 R25 2n2 5k1 R26 100 C46 C44 100n C45 10u 1n
T4
CD3 BB804 R27 5k6
J109
R17 47
C34 220n
R23 5R6 VSPLL P10
T2 BC848B R15 1k C36
R18 P16 470k R19 470k
3p9 S391D 10n
AMPREIN P14 D2 S391D C33 R28 3k9 P9 AMAGCO R22 470k
Bu1 Ant
L4 4u7 C35 10p
10n
D3 S391D
100n
30
T4260
4528D-AUDR-09/02
OSCBUF
MXAMIB
MXAMIA
MXFMIA
MXFMIB
GNDRF
VRVCO
VTUNE
VSPLL
OSCE
OSCB
AMLF
DAC1
DAC2
FMLF
SW1
T4260
Ordering Information
Extended Type Number Package Remarks
T4260IL T4260ILQ
SSO44 SSO44
Tube Taped and reeled
Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications
1
22
31
4528D-AUDR-09/02
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4528D-AUDR-09/02 xM

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